The present invention generally relates to a substrate for a semiconductor assembly and, in particular, relates to one such substrate including means for establishing interconnections between and among a plurality of individual semiconductor chips.
In order to accomplish very high density multifunction semiconductor devices, the semiconductor industry has taken divergent approaches. One approach is generally referred to as the fully integrated device. In a fully integrated device all of the active devices are formed within the semiconductor substrate using known integration techniques. In addition to the devices, all of the interconnects are routed, layed out and also formed within the semiconductor wafer. Although this approach has had a reasonable rate of success, the success rate rapidly decreases when the density of devices exceeds certain limits. Under such conditions not only does normal semiconductor integration defects result in totally non-functional devices, but the actual design and layout of the devices and the interconnections therefor create unusual heat dissipation difficulties and interelectrode effects.
The other approach taken by the semiconductor industry is generally referred to as a wafer scale assembly. In such an assembly a substrate, usually a semiconductor wafer, is provided with a plurality of interconnections predesigned and layed out to accomodate a plurality of active chips that are bonded or otherwise attached to the substrate. In such an assembly the active devices can be pretested and, frequently, if found defective subsequent to assembly, can be replaced. One of the drawbacks of such assemblies is that, at least to date, the interconnections formed in the substrate have been formed and routed according to the conventional semiconductor integration fabrication techniques. That is, if two points separated on the substrate are to be connected, a metallization path is formed therebetween. In addition, when other points are to be interconnected, metallization paths interconnecting those points must either be disposed to avoid interfering with any previously layed out paths or they must be provided by a multilayer technique so that they are electrically isolated from every other electrical path. Consequently, each semiconductor substrate for a particular wafer scale assembly is personalized to that particular assembly and each different wafer scale assembly requires a different semiconductor wafer layout or pattern of metallization path. Such a diversity of semiconductor substrates, although providing the beneficial effect of wafer scale semiconductor assemblies, nevertheless, requires a considerable amount of design time to avoid interferences between various paths within the substrate. Such design time extensions significantly increase the cost of each new wafer scale assembly developed.
Consequently, there is a considerable need for the provision of a uniform, or universal, wafer scale assembly substrate that not only allows a reduced expense during the development and manufacturing of an assembly, but additionally provides the ability to interconnect any two points thereon in an efficient inexpensive fashion.